프리다이빙 일정

I actually agree. We're going to encounter more relaxed ordering in multiprocessors. The query is, what do the hardware designers consider conservative? Forcing an interlock at each the beginning and Memory Wave finish of a locked section seems to be fairly conservative to me, but I clearly am not imaginative enough. The Pro manuals go into excruciating element in describing the caches and what keeps them coherent but don’t seem to care to say something detailed about execution or Memory Wave Method read ordering. The reality is that we don't have any way of figuring out whether or not we’re conservative enough. Zero outcome, and that the Pentium Pro simply had larger pipelines and write queues that exposed the behavior more typically. The Intel architect additionally wrote: Loosely talking, this implies the ordering of occasions originating from any one processor in the system, as observed by different processors, is at all times the same. Nonetheless, totally different observers are allowed to disagree on the interleaving of events from two or extra processors.

Future Intel processors will implement the same memory ordering mannequin. The declare that "different observers are allowed to disagree on the interleaving of events from two or more processors" is saying that the reply to the IRIW litmus take a look at can reply "yes" on x86, even though within the previous part we saw that x86 solutions "no." How can that be? The answer appears to be that Intel processors never truly answered "yes" to that litmus test, but at the time the Intel architects were reluctant to make any guarantee for future processors. What little textual content existed within the architecture manuals made almost no ensures in any respect, making it very troublesome to program against. The Plan 9 dialogue was not an remoted event. The Linux kernel developers spent over 100 messages on their mailing record starting in late November 1999 in related confusion over the guarantees offered by Intel processors.

In response to increasingly more individuals working into these difficulties over the decade that followed, a gaggle of architects at Intel took on the duty of writing down useful ensures about processor Memory Wave conduct, for both current and future processors. CC), intentionally weaker than TSO. CC was "as robust as required however no stronger." In particular, the mannequin reserved the proper for x86 processors to reply "yes" to the IRIW litmus test. Unfortunately, the definition of the memory barrier was not strong sufficient to reestablish sequentially-consistent Memory Wave Method semantics, even with a barrier after each instruction. Revisions to the Intel and AMD specifications later in 2008 assured a "no" to the IRIW case and strengthened the memory limitations however still permitted unexpected behaviors that appear like they couldn't come up on any affordable hardware. To handle these issues, Owens et al. 86-TSO model, based on the earlier SPARCv8 TSO mannequin. On the time they claimed that "To the best of our data, x86-TSO is sound, is strong enough to program above, and is broadly according to the vendors’ intentions." A few months later Intel and AMD launched new manuals broadly adopting this mannequin.

It appears that every one Intel processors did implement x86-TSO from the start, even though it took a decade for Intel to decide to decide to that. In retrospect, it is obvious that the Intel and AMD architects had been struggling with exactly how to jot down a memory model that left room for future processor optimizations while still making helpful guarantees for compiler writers and meeting-language programmers. "As strong as required however no stronger" is a difficult balancing act. Now let’s look at an much more relaxed memory model, the one found on ARM and Power processors. CC. The conceptual mannequin for ARM and Energy programs is that each processor reads from and writes to its personal full copy of memory, and each write propagates to the other processors independently, with reordering allowed as the writes propagate. Right here, there isn't any total store order. Not depicted, every processor can also be allowed to postpone a read till it wants the consequence: a learn may be delayed until after a later write.

In the ARM/Power mannequin, we are able to consider thread 1 and thread 2 every having their own separate copy of memory, with writes propagating between the memories in any order in any respect. 0. This end result reveals that the ARM/Energy memory mannequin is weaker than TSO: it makes fewer necessities on the hardware. On x86 (or other TSO): sure! On ARM/Power, the writes to x and y is likely to be made to the local reminiscences however not yet have propagated when the reads happen on the other threads. Can Threads three and four see x and y change in different orders? On ARM/Energy, different threads may find out about different writes in several orders. They don't seem to be guaranteed to agree about a complete order of writes reaching predominant memory, so Thread three can see x change earlier than y while Thread 4 sees y change earlier than x. Can every thread’s read happen after the other thread’s write? 1 execute before the 2 reads. Although both the ARM and Energy memory models enable this outcome, Maranget et al.